1. Field of the Invention
This invention relates to self-refreshing static random access memories (SRAMs) that have dynamic random access memory (DRAM) internal memory cells and, more particularly, to circuits for testing certain performance parameters of the DRAM cells.
2. Prior Art
A self-refreshing SRAM is a memory device that internally uses dynamic random access memory DRAM cells and that requires periodic refreshing of those DRAMS cells in a series of internal refresh cycles. A self-refreshing SRAM periodically refreshes its internal dynamic memory cells using an internal system that has an arbitration circuit that arbitrates between internal memory refresh requests and external read/write requests. The arbitration circuit grants access to memory rows for either refreshing or data read/write by providing one of two row access select RAS signals. One RAS signal is a normal row access select NRAS signal that provides access to memory rows during normal read/write operations. The other RAS signal is a refresh row access select RRAS signal that provides access to memory rows during internal refresh cycles.
A conventional self-refreshing SRAM cannot precisely control initiation of an internal refresh operation because all refresh operations are automatically internally controlled by the arbitration circuit. Therefore, the real refresh time or the maximum refresh capability of the DRAM cells cannot be measured exactly.
Consequently, a need exists for a technique that allows the real refresh time and maximum refresh capability of the internal DRAM cells in a self-refreshing DRAM to be measured exactly.